A system widely used in household electric appliances, office equipment, and so on is generally a built-in system composed of hardware and software.
The built-in system is composed of an ASIC, a processor, a memory, and so on. The ASIC may be replaced with an FPGA.
ASIC is an abbreviation for Application Specific Integrated Circuit. FPGA is an abbreviation for Field-Programmable Gate Array.
In recent years, a built-in system is provided in the form of SoC.
The SoC is a single semiconductor chip in which all the functions necessary for the operation of the system are implemented.
In the design of the built-in system, it is necessary to divide the specification describing the processing function of the entire system into a part to be made as hardware with using the ASIC or the like and a part to be made as software in the form of a program which is executed by a processor. This division is called software/hardware function division.
Also, in design of the built-in system, it is necessary to study how to implement a plurality of divided functions on the SoC so that a desired performance can be achieved. Such design is called architecture design.
Patent Literature 1 discloses a device which executes software/hardware function division by calculating the loads of processes from the specification describing the processing function of the entire system and designing a process whose load exceeds a threshold value, as hardware.
Patent Literature 2 discloses a device which generates a communication interface by automatically determining a connection bus between modules based on previously given hardware configuration information. The hardware configuration information is information including connection information such as an on-chip bus and direct connection.
If Patent Literature 1 and Patent Literature 2 are combined, automatic SoC generation from algorithm C can be achieved. Algorithm C is an algorithm described in C language.
In order to automatically generate SoC, however, it is necessary to study in advance SoC architecture to realize a system specification. More specifically, it is necessary to study in advance the configuration of a module that constitutes the hardware provided to the SoC.
Hardware module configuration is conventionally determined by conducting module division according to the experience of the designer. In addition, the module division is conventionally conducted from a viewpoint such as a parallelization of process operations and common circuit use by analyzing the system specification of the process to be made as hardware.
However, it is very difficult to conduct optimal module division according to the experience of the designer, and accordingly there is a fear that large rework may occur. A large rework occurs when it is proved in the post-process of the SoC design that an expected performance has not been achieved, or the circuit scale may exceed the chip area.